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LT3050 1 3050f typical application description 100ma, low noise linear regulator with precision current limit and diagnostic functions the lt ? 3050 is a micro-power, low noise, low dropout voltage (ldo) linear regulator. the device supplies 100ma of output current with a dropout voltage of 340mv. a 10nf bypass capacitor reduces output noise to 30v rms in a 10hz to 100khz bandwidth and soft-starts the reference. the LT3050s 45v input voltage rating combined with its precision current limit and diagnostic functions make the ic an ideal choice for robust, high reliability applications. a single resistor programs the LT3050s current limit, accurate to 5% over a wide input voltage and temperature range. a single resistor programs the LT3050s minimum output current monitor, useful for detecting open-circuit conditions. the current monitor function sources a current equal to 1/100th of output current. a logic fault pin asserts low if the LT3050 is in current limit, operating below its minimum output current (open-circuit) or is in thermal shutdown. the LT3050 optimizes stability and transient response with low esr ceramic capacitors, requiring a minimum of 2.2f. the LT3050 is available as an adjustable device with an output voltage range down to the 0.6v reference. the LT3050 is available in the thermally-enhanced 12-lead 3mm 2mm dfn and msop packages. 5v supply with 100ma precision current limit, 10ma i min features applications n output current: 100ma n dropout voltage: 340mv n input voltage range: 1.6v to 45v n programmable precision current limit: 5% n programmable minimum i out monitor n output current monitor: 1/100 th of i out n fault indicator : current limit, minimum i out or thermal limit n low noise: 30v rms (10hz to 100khz) n adjustable output (v ref = v out(min) = 0.6v) n output tolerance: 2% over line, load and temperature n stable with low esr, ceramic output capacitors (2.2f minimum) n shutdown current: <1a n reverse-battery, reverse-output and reverse-current protection n thermal limit protection n 12-lead 3mm 2mm dfn and msop packages n protected antenna supplies n automotive telematics n industrial applications (trucks, forklifts, etc.) n high reliability applications 1f 12v v in in i mon i max i min fault shdn gnd out adj ref/byp LT3050 5v 2.2f 0.1f 10nf 1% 442k 1% 60.4k 3k (adc full scale = 3v) to p adc 0.1f 11.3k (threshold = 10ma) 10nf 1.15k (threshold = 100ma) 120k 3050 ta01 external current limit r imax = 1.15k l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. temperature (c) current limit fault threshold (ma) 105 100 101 102 103 104 98 99 3050 ta01a 95 96 97 C75 C50 C25 0 C25 50 75 100 125 150 175 v in = 5.6v v in = 12v v in = 15v v out = 5v
LT3050 2 3050f pin configuration absolute maximum ratings in pin voltage ........................................................ 50v out pin voltage ..................................................... 50v input-to-output differential voltage ....................... 50v adj pin voltage ..................................................... 50v ref/byp pin voltage ........................................?0.3v, 1v shdn pin voltage ...................................................50v i mon pin voltage ..............................................?0.3v, 7v i min pin voltage ...............................................?0.3v, 7v i max pin voltage ...............................................?0.3v, 7v (note 1) 1 2 3 4 5 6 ref/byp i min fault shdn in in 12 11 10 9 8 7 i mon i max gnd adj out out top view mse package 12-lead plastic msop 13 gnd t jmax = 125c, s 2mm) plastic dfn ref/byp i min fault shdn in in i mon i max gnd adj out out 13 gnd 8 7 10 9 11 12 5 6 4 2 3 1 t jmax = 125c,
LT3050 3 3050f electrical characteristics parameter conditions min typ max units minimum input voltage (notes 3, 11) i load = 100ma l 1.6 2.2 v adj pin voltage (notes 3, 4) v in = 2.2v, i load = 1ma 2.2v < v in < 15v, 1ma < i load < 100ma (note 15) l 594 588 600 606 612 mv mv line regulation (note 3) v in = 2.2v to 45v, i load = 1ma l 0.25 3 mv load regulation (note 3) v in = 2.2v, i load = 1ma to 100ma l 0.2 4 mv dropout voltage v in = v out(nominal) (notes 5, 6) i load = 1ma i load = 1ma l 110 150 220 mv mv i load = 10ma i load = 10ma l 195 240 340 mv mv i load = 50ma i load = 50ma l 280 330 450 mv mv i load = 100ma i load = 100ma l 340 400 550 mv mv gnd pin current v in = v out(nominal) + 0.6v (notes 6, 7, 11) i load = 0ma i load = 1ma i load = 10ma i load = 50ma i load = 100ma l l l l l 45 60 175 0.85 2.2 90 160 370 2 5.2 a a a ma ma quiescent current in shutdown v in = 12v, v shdn = 0v 0.17 1 a adj pin bias current (notes 3, 12) v in = 12v l 12.5 60 na output voltage noise c out = 10f, i load = 100ma, v out = 600mv, bw = 10hz to 100khz 90 v rms output voltage noise c out = 10f, c byp = 0.01f, i load = 100ma, v out = 600mv bw = 10hz to 100khz 30 v rms shutdown threshold v out = off to on v out = on to off l l 0.3 0.7 0.6 1.5 v v shdn pin current (note 13) v shdn = 0v v shdn = 45v l l 0.9 1 3 a a ripple rejection (note 3) v in Cv out = 2v (avg), v ripple = 0.5v p-p , f ripple = 120hz, i load = 100ma 70 85 db fault pin logic low voltage v in = 2.2v, fault asserted, i fault = 100a l 140 250 mv fault pin leakage current fault = 5v, fault not asserted 0.01 1 a input reverse leakage current v in = C45v, v out = 0 l 300 a reverse output current (note 14) v out = 1.2v, v in = 0 0.2 10 a internal current limit (note 3) v in = 2.2v, v out = 0, i max pin grounded v out = C5% l 110 240 ma external programmed current limit (note 8) 5.6v < v in < 15v, v out = 5v, r imax = 2.26k fault pin threshold l 47.8 50.4 52.9 ma 5.6v < v in < 15v, v out = 5v, r imax = 1.5k fault pin threshold l 72.1 75. 9 79.7 ma 5.6v < v in < 15v, v out = 5v, r imax = 1.15k fault pin threshold l 94.4 99.3 104.3 ma the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 2)
LT3050 4 3050f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. absolute maximum input-to-output differential voltage is not achievable with all combinations of rated in pin and out pin voltages. with the in pin at 50v, the out pin may not be pulled below 0v. the total differential voltage from in to out must not exceed 50v. note 2: the LT3050 is tested and speci? ed under pulse load conditions such that t j ~ t a . the LT3050e is 100% production tested at t a = 25c. performance at C40c and 125c is assured by design, characterization and correlation with statistical process controls. the LT3050i is guaranteed over the full C40c to 125c operating junction temperature range. the LT3050mp is 100% tested over the C55c to 125c operating junction temperature range. note 3: the LT3050 is tested and speci? ed for these conditions with adj pin connected to the out pin. note 4: maximum junction temperature limits operating conditions. regulated output voltage speci? cations do not apply for all possible combinations of input voltage and output current. if operating at the maximum input voltage, limit the output current range. if operating at the maximum output current, limit the input voltage range. note 5: dropout voltage is the minimum differential in-to-out voltage needed to maintain regulation at a speci? ed output current. in dropout, the output voltage equals (v in - v dropout ). for some output voltages, minimum input voltage requirements limit dropout voltage. note 6: to satisfy minimum input voltage requirements, the LT3050 is tested and speci? ed for these conditions with an external resistor divider (60k bottom, 440k top) which sets v out to 5v. the external resistor divider adds 10a of dc load on the output. this external current is not factored into gnd pin current. parameter conditions min typ max units minimum i min threshold accuracy (note 9) 5.6v < v in < 15v, v out = 5v, r imin = 110k l 0.9 1 1.1 ma i min threshold accuracy (note 9) 5.6v < v in < 15v, v out = 5v, r imin = 11.3k l 91011 ma current monitor ratio (note10) ratio = i out /i mon v imon = v out = 5v, 5.6v < v in < 15v i load = 5ma, 25ma, 50ma, 75ma, 100ma l 95 100 105 note 7: gnd pin current is tested with v in = v out(nominal) + 0.5v and a current source load. gnd pin current increases in dropout. see gnd pin current curves in the typical performance characteristics section. note 8: current limit varies inversely with the external resistor value tied from the i max pin to gnd. for detailed information on how to set the i max pin resistor value, please see the operation section. if a programmed current limit is not needed, the i max pin must be tied to gnd and internal protection circuitry implements short-circuit protection as speci? ed. note 9: the i min fault condition asserts if the output current falls below the i min threshold de? ned by an external resistor from the i min pin to gnd. for detailed information on how to set the i min pin resistor value, please see the operation section. i min settings below the minimum i min accuracy speci? cation in the electrical characteristics section are not guaranteed to 10% tolerance. if the i min fault condition is not needed, the i min pin must be left ? oating (unconnected). note 10: the current monitor ratio varies slightly when v imon v out . for detailed information on how to calculate the output current from the i mon pin, please see the operation section. if the current monitor function is not needed, the i mon pin must be tied to gnd. note 11: to satisfy requirements for minimum input voltage, current limit is tested at v in = v out(nominal) +1v or v in = 2.2v, whichever is greater. note 12: adj pin bias current ? ows out of the adj pin: note 13: shdn pin current ? ows into the shdn pin. note 14: reverse output current is tested with the in pin grounded and the out pin forced to the speci? ed voltage. this current ? ows into the out pin and out of the gnd pin. note 15: 100ma of output current does not apply to the full range of input voltage due to the internal current limit foldback. electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 2)
LT3050 5 3050f typical performance characteristics quiescent current adj pin voltage 5v quiescent current gnd pin current gnd pin current vs i load shdn pin threshold typical dropout voltage guaranteed dropout voltage dropout voltage t j = 25c, unless otherwise noted. output current (ma) dropout voltage (mv) 600 300 350 400 450 550 500 250 3050 g01 0 50 100 150 200 0 10 20 30 40 50 60 70 80 90 100 t j 125c t j 25c output current (ma) dropout voltage (mv) 600 300 350 400 450 550 500 250 3050 g02 0 50 100 150 200 0 10 20 30 40 50 60 70 80 90 100 t j = 125c =test points t j = 25c temperature (c) C75 0 dropout voltage (mv) 450 500 550 400 350 300 250 200 150 100 50 600 C50 75 100 125 150 175 C25 0 25 3050 g03 50 i l = 100ma i l = 50ma i l = 10ma i l = 1ma temperature (c) C75 0 quiescent current (a) 50 60 70 40 30 20 10 80 C50 75 100 125 150 175 C25 0 25 3050 g04 50 v in = v shdn = 12v v out = 5v i l = 5a v in = 12v all other pins = 0v v in (v) quiescent current (a) 100 50 60 80 70 90 40 30 3050 g06 0 10 20 0 5 10 15 20 25 30 35 40 45 v shdn = v in , r l = 500k v shdn = 0 v , r l = 0 input voltage (v) gnd pin current (ma) 2.50 1.50 1.75 2.00 2.25 1.25 3050 g07 0 0.25 0.50 0.75 1.00 012 3456789101112 v out = 5v r l = 50, i l = 100ma r l = 100, i l = 50ma r l = 500, i l = 10ma r l = 5k, i l = 1ma i load (ma) gnd pin current (ma) 5.0 2.0 2.5 3.0 3.5 4.5 4.0 1.5 3050 g08 0 0.5 1.0 0102030405060708090100 v in = 5.6v v out = 5v temperature (c) shdn pin threshold (v) 1.5 0.4 0.5 0.6 0.7 0.9 1.0 1.1 1.2 1.3 1.4 0.8 0.3 3050 g09 0 0.1 0.2 C75 C50 0 C25 25 50 75 100 125 150 175 i l = 1ma off to on on to off temperature (c) C75 588 adj pin voltage (mv) 606 608 610 604 602 600 598 596 594 592 590 612 C50 75 100 125 150 175 C25 0 25 3050 g05 50
LT3050 6 3050f internal current limit internal current limit internal current limit vs output voltage reverse output current reverse output current input ripple rejection shdn pin input current shdn pin input current adj pin bias current typical performance characteristics t j = 25c, unless otherwise noted. temperature (c) shdn pin input current (a) 3.0 1.0 2.0 2.5 1.5 0.5 3050 g10 0 C75 C50 C25 0 25 50 75 100 125 150 175 v shdn = 45v shdn pin voltage (v) shdn pin input current (a) 2.0 0.6 1.2 1.4 1.6 1.8 0.8 1.0 0.2 0.4 3050 g11 0 0 1020304050 temperature (c) adj pin bias current (na) 50 15 30 35 40 45 20 25 5 10 3050 g12 0 C75 C50 C25 0 25 50 75 100 125 150 175 v out (v) i out (a) 1.0 0.3 0.6 0.7 0.8 0.9 0.4 0.5 0.1 0.2 3050 g16 0 0 1020304050 all pins grounded except for out frequency (hz) ripple rejection (db) 90 40 50 60 70 80 30 3050 g18 0 10 20 10 100 1k 10k 100k 1m 10m i l = 100ma c out = 10f v out = 5v v in = 5.8v + 50mv rms ripple c ref/byp = 0 c ref/byp = 100pf c ref/byp = 10nf temperature (c) current limit (ma) 350 100 200 250 300 150 50 3050 g13 0 C75 C50 C25 0 25 50 75 100 125 150 175 v in = 12v v out = 0v input/output differential (v) current limit (ma) 250 50 100 125 150 175 200 225 75 25 3050 g14 0 0 5 10 15 20 25 30 35 40 45 t j = C55c t j = C40c t j = 25c t j = 125c current limit at fault threshold output voltage (v) current limit (ma) 225 50 100 125 150 175 200 75 25 3050 g15 0 0 5 10 15 20 25 30 35 40 45 t j = C55c t j = C40c t j = 25c t j = 125c v in C v out(nominal) = 1v current limit at fault threshold temperature (c) current(a) 50 10 20 25 30 35 40 45 15 5 3050 g17 0 C75 C50 C25 0 25 50 75 100 125 150 175 v out = v adj = 1.2v v in = 0 i adj i out
LT3050 7 3050f output noise spectral density c ref/byp = 0 output noise spectral density vs c ref/byp rms output noise vs load current vs c ref/byp rms output noise vs load current c ref/byp = 10nf input ripple rejection minimum input voltage load regulation typical performance characteristics t j = 25c, unless otherwise noted. frequency (hz) input ripple rejection (db) 90 40 50 60 70 80 30 3050 g19 0 10 20 10 100 1k 10k 100k 1m 10m i l = 100ma c ref/byp = 100pf v out = 5v v in = 5.8v + 50mv rms ripple c out = 2.2f c out = 10f temperature (c) minimum input voltage (v) 2.2 1.2 1.4 1.6 1.8 2.0 1.0 3050 g20 0 0.2 0.4 0.6 0.8 C75 C50 C25 0 25 50 75 100 125 150 175 i l =100ma temperature (c) load regulation (mv) 4 1 2 3 0 3050 g21 C4 C2 C1 C3 C75 C50 0 25 C25 50 75 100 125 150 175 i l = 1ma to 100ma v out = 0.6v v in = 2.2v load current (ma) 0.01 0 output noise voltage (v rms ) 40 30 20 10 110 100 90 80 70 60 50 10 1 100 3050 g24 0.1 v out = 0.6v c out = 10f c ref/byp = 0 c ref/byp = 10pf c ref/byp = 100pf c ref/byp = 1nf c ref/byp = 10nf c ref/byp = 100nf load current (ma) 0.01 0 output noise voltage (v rms ) 50 40 30 20 10 170 120 130 140 150 160 110 100 90 80 70 60 10 1 100 3050 g25 0.1 v out = 5v v out = 3.3v v out = 1.2v v out = 2.5v v out = 1.8v v out = 1.5v v out = 0.6v f out = 10hz to 100khz c out = 10f temperature (c) ripple rejection (db) 100 20 40 50 60 70 80 90 30 10 3050 g19a 0 C75 C50 C25 0 25 50 75 100 125 150 175 i l = 100ma v out = 5v v in = 5.8v + 0.5v p-p ripple at f = 120hz c out = 10f c ref/byp = 10nf frequency (hz) output noise spectral density (v/ hz ) 10 1 3050 g22 0.01 0.1 10 100 1k 10k 100k i l = 100ma c out = 10f v out = 1.5v v out = 1.2v v out = 0.6v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v frequency (hz) 10 0.01 output noise spectral density (v/ hz ) 1 0.1 10 10k 1k 100k 3050 g23 100 v out = 5v c ref/byp = 10nf c ref/byp = 1nf v out = 0.6v c out = 10f i l = 100ma c ref/byp = 100pf ripple rejection vs temperature startup time vs ref/byp capacitor ref/byp capacitor (nf) startup time (ms) 60 50 40 30 3050 g33 0 10 20 0 102030405060708090100
LT3050 8 3050f shdn transient response c ref/byp = 10nf external current limit r imax = 2.26k external current limit r imax = 1.5k external current limit r imax = 1.5k transient response transient response (load dump) shdn transient response c ref/byp =0 typical performance characteristics t j = 25c, unless otherwise noted. v out 100mv/div i out 50ma/div 200s/div 3050 g28 i out = 10ma to 100ma v in = 6v v out = 5v c out = c in = 10f out 5v/div i l =100ma ref/byp 500mv/div shdn 1v/div 2ms/div 3050 g30 out 5v/div i l = 100ma ref/byp 500mv/div shdn 1v/div 2ms/div 3050 g31 temperature (c) current limit fault threshold (ma) 52.8 50.3 50.8 51.3 51.8 52.3 49.3 49.8 3050 g34 47.8 48.3 48.8 C75 C50 0 25 C25 50 75 100 125 150 175 v out = 5v v in = 5.6v v in = 12v v in = 15v temperature (c) current limit fault threshold (ma) 79.50 75.75 76.50 77.25 78.00 78.75 74.25 75.00 3050 g35 72.00 72.75 73.50 C75 C50 C25 0 25 50 75 100 125 150 175 v out = 5v v in = 5.6v v in = 12v v in = 15v temperature (c) current limit fault threshold (ma) 105 100 101 102 103 104 98 99 3050 g36 95 96 97 C75 C50 C25 0 C25 50 75 100 125 150 175 v in = 5.6v v in = 12v v in = 15v v out = 5v 3050 g29 v out 20mv/div v in 10v/div 1ms/div 45v 12v v out = 5v i out = 50ma c out = 2.2f 5v 10hz to 100khz output noise c ref/byp = 0 1ms/div c out = 10f i l = 100ma v out 500v/div 3050 g27 5v 10hz to 100khz output noise c ref/byp = 10nf 1ms/div c out = 10f i l = 100ma v out 500v/div 3050 g26
LT3050 9 3050f i out /i mon current ratio v out = 5v, v in = 5.6v minimum output current threshold r imin = 11.3k minimum output current threshold r imin = 110k i out /i mon current ratio v out = 5v, v in = 12v typical performance characteristics t j = 25c, unless otherwise noted. temperature (c) minimum output current threshold (ma) 11.00 10.25 10.50 10.75 9.75 10.00 3050 g38 9.00 9.25 9.50 C75 C50 C25 0 25 50 75 100 125 150 175 v out = 5v v in = 5.6v v in = 12v v in = 15v temperature (c) minimum output current threshold (ma) 1.100 1.025 1.050 1.075 0.975 1.000 3050 g37 0.900 0.925 0.950 C75 C50 C25 0 25 50 75 100 125 150 175 v out = 5v v in = 15v v in = 12v v in = 5.6v i out (ma) i out /i mon current ratio 102 97 98 99 100 101 95 96 3050 g39 92 93 94 0 25 50 75 100 125 v imon = 1v v imon = 0v v imon = 2v v imon = 3v v imon = 4v v imon = 5v i out (ma) i out /i mon current ratio 102 97 98 99 100 101 95 96 3050 g40 92 93 94 0 25 50 75 100 125 v imon = 1v v imon = 0v v imon = 2v v imon = 3v v imon = 5v v imon = 4v i out /i mon current ratio v out = 5, v in = 5.6v i out (ma) i out /i mon current ratio 102 96 97 98 99 100 94 95 3050 g41 91 92 93 0 25 50 75 100 125 125c 25c C55c v imon = 5v v imon = 0v i out (ma) i out /i mon current ratio 103 98 9 100 101 102 96 97 3050 g42 93 94 95 0 25 50 75 100 125 125c 25c C55c v imon = 5v v imon = 0v i out (ma) %error of calculation 5 0 1 2 3 4 C2 C1 3050 g43 C5 C4 C3 0 25 50 75 100 125 i out = i monr ? ? v imon r imon 70 + v in C v out 70 + v in C v out (see page 12 for details) v in =5.6v, r imon =1k v in =5.6v, r imon =2k v in =5.6v, r imon =3k v in =12v, r imon =1k v in =12v, r imon =2k v in =12v, r imon =3k i out /i mon current ratio v out = 5v, v in = 12v i out calculated from i mon v out = 5v
LT3050 10 3050f pin functions ref/byp (pin 1): bypass/soft-start. connecting a single capacitor from this pin to gnd bypasses the LT3050s reference noise and soft-starts the reference. a 10nf bypass capacitor typically reduces output voltage noise to 30v rms in a 10hz to 100khz bandwidth. soft-start time is directly proportional to the ref/byp capacitor value. if the LT3050 is placed in shutdown, ref/byp is actively pulled low by an internal device to reset soft-start. if low noise or soft-start performance is not required, this pin must be left ? oating (unconnected). do not drive this pin with any active circuitry. because the ref/byp pin is the reference input to the error ampli? er, stray capacitance at this point should be minimized. special attention should be given to any stray capacitances that can couple external signals onto the ref/byp pin producing undesirable output transients or ripple. a minimum ref/byp capacitance of 100pf is recommended. i min (pin 2): minimum output current programming pin. this pin is the collector of a pnp current mirror that outputs 1/200th of the power pnp load current. this pin is also the input to the minimum output current fault comparator. connecting a resistor between i min and gnd sets the minimum output current fault threshold. for detailed information on how to set the i min pin resistor value, please see the operation section. a small external decoupling capacitor (10nf minimum) is required to improve i min psrr. if minimum output current programming is not required, the i min pin must be left ? oating (unconnected). fault (pin 3): fault pin. this is an open collector logic pin which asserts during current limit, thermal limit or a minimum current fault condition. the maximum low logic output level is de? ned for sinking 100a of current. off state logic may be as high as 45v without damaging internal circuitry regardless of the v in used. shdn (pin 4): shutdown. pulling the shdn pin low puts the LT3050 into a low power state and turns the output off. drive the shdn pin with either logic or an open collector/drain with a pull-up resistor. the resistor supplies the pull-up current to the open collector/drain logic, normally several microamperes, and the shdn pin current, typically less than 2a. if unused, connect the shdn pin to in. the LT3050 does not function if the shdn pin is not connected. the shdn pin cannot be driven below gnd unless tied to the in pin. if the shdn pin is driven below gnd while in is powered, the output may turn on. shdn pin logic cannot be referenced to a negative rail. in (pin 5,6): input. these pins supply power to the device. the LT3050 requires a local in bypass capacitor if it is located more than six inches from the main input ? lter capacitor. in general, battery output impedance rises with frequency, so adding a bypass capacitor in battery powered circuits is advisable. a minimum input of 1f generally suf? ces. out (pin 7,8): output. these pins supply power to the load. stability requirements demand a minimum 2.2f ceramic output capacitor to prevent oscillations. large load transient applications require larger output capacitors to limit peak voltage transients. see the applications information section for details on transient response and reverse output characteristics. permissible output voltage range is 600mv to 44.5v. adj (pin 9): adjust. this pin is the error ampli? ers inverting terminal. its typical bias of 16na current ? ows out of the pin (see curve of adj pin bias current vs. temperature in the typical performance characteristics section). the typical adj pin voltage is 600mv referenced to gnd. gnd (pin 10, exposed pad pin 13): ground. the exposed pad of the dfn and msop packages is an electrical connection to gnd. to ensure proper electrical and thermal performance, solder pin 13 to the pcb ground and tie directly to pin 10. connect the bottom of the output voltage setting resistor divider directly to gnd (pin 10) for optimum load regulation performance. i max (pin 11): precision current limit programming pin. this pin is the collector of a current mirror pnp that is 1/200 th the size of the output power pnp. this pin is also the input to the current limit ampli? er. current limit threshold is set by connecting a resistor between the i max pin and gnd.
LT3050 11 3050f for detailed information on how to set the i min pin resistor value, please see the operation section. the i max pin requires a 10nf decoupling capacitor to ground. if not used, tie i max to gnd. i mon (pin 12): output current monitor. this pin is the collector of a pnp current mirror that outputs 1/100 th pin functions of the power pnp current. when out = i mon , the pin current exactly equals 1/100 th that of the output current. for detailed information on how to calculate the output current from the i mon pin, please see the operation section. the i mon pin requires a small (22nf minimum) external decoupling capacitor. if the i mon pin is not used, it must be tied to gnd. block diagram + C + C + C 4 9 11 12 2 3 1 in 5, 6 r1 d1 q3 qi min 1/200 qi mon 1/100 qi max 1/200 qpower 1 i max i min fault i mon qfault u1 gnd 10, 13 ref/byp shdn adj 30k r4 ideal diode d3 q2 d2 error amplifier thermal/ current limits current limit amplifier 100k r3 i min comparator 100k r2 600mv reference 3050 bd01 out 7, 8 + C
LT3050 12 3050f operation i mon pin operation (current monitor) the i mon pin is the collector of a pnp which mirrors the LT3050 output pnp at a ratio of 1:100 (see block diagram on page 11). the current sourced by the i mon pin is ~1/100 th of the current sourced by the out pin when the i mon and out pin voltages are equal and the device is not operating in dropout. if the i mon and out pin voltages are not the same, the ratio deviates from 1/100 due to the early voltages of the i mon and out pnps according to the equation: i imon i out 1 i monr v 70 v in v imon 70 v in v out early voltage compensation 12 44 43 444 where the early voltage of the pnps is 70v and i monr is a variable which represents the i out to i mon current ratio. i monr varies with v in to v out voltage according to the empirically derived equation: i monr = 97 + 5 ? log 10 (1+v in C v out ) for (v in C v out ) 0.5 i monr = 96 + 2 ? (v in C v out ) for (v in C v out ) < 0.5 the i mon pin current can be converted into a voltage for use by monitoring circuitry simply by connecting the i mon pin to a resistor. connecting a resistor from i mon to gnd converts the i mon pin current into a voltage that can be monitored by circuitry such as an adc. for example, a 1.2k resistor results in a i mon pin voltage of 1.2v for an output current of 100ma and an output voltage of 1.2v. the output current of the device can be calculated from the i mon pin voltage by the following equation: i out i monr i out i mon ratio { v v imon r imon i imon 123 v 70 v in v out 70 v in v imon early voltagecompensation 12 44 43 444 a small decoupling capacitor (22nf minimum) from i mon to gnd is required to improve i mon pin power supply rejection. if the current monitor is not needed, it must be tied to gnd. open circuit detection (i min pin) the i min pin is the collector of a pnp which mirrors the LT3050 output at a ratio of approximately 1:200 (see block diagram on page 11). the i min fault comparator asserts the fault pin if the i min pin voltage is below 0.6v. this low output current fault threshold voltage (i open ) is set by attaching a resistor from i min to gnd. r iv i imin open out open = 119 85 1 68 36 8 .C(.C.? )? this equation is empirically derived and partially compensates for early voltage effects in the i min current mirror. it is valid for an input voltage range from 0.6v above the output to 10v above the output. it is valid for output voltages up to 12v. the accuracy of this equation for setting the resistor value is approximately 2%. unit values are amps, volts, and ohms. if the open circuit detection function is not needed, the i min pin must be left ? oating (unconnected). a small decoupling capacitor (10nf minimum) from i min to gnd is required to improve i min pin power supply rejection and to prevent fault pin glitches. see the typical performance characteristics section for additional information.
LT3050 13 3050f external programmable current limit (i max pin) the i max pin is the collector of a pnp which mirrors the LT3050 output at a ratio of approximately 1:200 (see block diagram). the i max pin is also the input to the precision current limit ampli? er. if the output load increases to the point where it causes the i max pin voltage to reach 0.6v, the current limit ampli? er takes control of output regulation so that the i max pin clamps at 0.6v, regardless of the output voltage. the current limit threshold (i limit ) is set by attaching a resistor (r imax ) from i max to gnd: r 119.22 0.894 v i imax out limit = < ? this equation is empirically derived and partially compensates for early voltage effects in the i max current mirror. it is valid for an input voltage range from 0.6v above the output to 10v above the output. it is valid for output voltages up to 12v. the accuracy of this equation for setting the resistor value is approximately 1%. unit values are amps, volts, and ohms. in cases where the in to out voltage exceeds 10v, fold- back current limit will lower the internal current level limit, possibly causing it to preempt the external programmable current limit. see the internal current limit vs v in C v out graph in the typical performance characteristics section. if the external programmable current limit is not needed, the i max pin must be connected to gnd. the i max pin operation requires a 10nf decoupling capacitor. see the typical performance characteristics section for additional information. fault pin operation the fault pin is an open collector logic pin which asserts during internal current limit, precision current limit, thermal limit, or a minimum current fault. there is no internal pull-up on the fault pin; an external pull-up resistor is required. the fault pin provides drive for up to 100a of pull-down current. off state logic may be as high as 45v, regardless of the input voltage used. when asserted, the fault pin drive circuitry adds 50a (nominal) of gnd pin current. depending on the i min capacitance, byp capacitance, and out capacitance, the fault pin may assert during startup. consideration should be given to masking the fault signal during startup. the fault pin circuitry is inactive (not asserted) during shutdown and when the out pin is pulled above the in pin. operation in dropout the LT3050 contains circuitry which prevents the pnp output power device from saturating in dropout. this also keeps the i mon , i min , and i max current mirrors functioning accurately, even in dropout. however, this anti-saturation circuitry becomes less active at lower output currents, so there is some degradation of current mirror function for output currents less than 10ma.
LT3050 14 3050f the LT3050 is a micropower, low noise and low dropout voltage, 100ma linear regulator with micropower shutdown, programmable current limit, and diagnostic functions. the device supplies up to 100ma at a typical dropout voltage of 340mv and operates over a 2.2v to 45v input range. a single external capacitor can provide low noise reference performance and output soft-start functionality. for example, connecting a 10nf capacitor from the ref/byp pin to gnd lowers output noise to 30v rms over a 10hz to 100khz bandwidth. t his capacitor also soft-starts the reference and prevents output voltage overshoot at turn-on. the LT3050s quiescent current is merely 45a but provides fast transient response with a minimum low esr 2.2f ceramic output capacitor. in shutdown, quiescent current is less than 1a and the reference soft-start capacitor is reset. the LT3050 optimizes stability and transient response with low esr, ceramic output capacitors. the regulator does not require the addition of esr as is common with other regulators. the LT3050 typically provides 0.1% line regulation and 0.1% load regulation. internal protection circuitry includes reverse-battery protection, reverse- output protection, reverse-current protection, current limit with fold-back and thermal shutdown. this bullet-proof protection set makes it ideal for use in battery-powered, automotive and industrial systems. in battery backup applications where the output is held up by a backup battery and the input is pulled to ground, the LT3050 acts like it has a diode in series with its output and prevents reverse current ? ow. adjustable operation the LT3050 has an output voltage range of 0.6v to 44.5v. the output voltage is set by the ratio of two external resistors, as shown in figure 1. the device servos the output to maintain the adj pin voltage at 0.6v referenced applications information figure 1. adjustable operation to ground. the current in r1 is then equal to 0.6v/r1, and the current in r2 is the current in r1 minus the adj pin bias current. v in v out in out LT3050 shdn adj gnd 3050 f01 r2 r1 vv r r ir vv i out adj adj ad =+ 2 | () ? = 06 1 2 1 2 06 .? . j j na at c output range v to v = = 16 25 0 6 44 5 .. the adj pin bias current, 16na at 25c, ? ows from the adj pin through r1 to gnd. calculate the output voltage using the formula in figure 1. the value of r1 should be no greater than 124k to provide a minimum 5a load current so that output voltage errors, caused by the adj pin bias current, are minimized. note that in shutdown, the output is turned off and the divider current is zero. curves of adj pin voltage vs temperature and adj pin bias current vs temperature appear in the typical performance characteristics section. the LT3050 is tested and speci? ed with the adj pin tied to the out pin, yielding v out = 0.6v. speci? cations for output voltages greater than 0.6v are proportional to the ratio of the desired output voltage to 0.6v: v out /0.6v. for example, load regulation for an output current change of 1ma to 100ma is C0.2mv (typical) at v out = 0.6v. at v out = 12v, load regulation is: 12 06 02 4 v v mv mv . ?. ? ? () =
LT3050 15 3050f table 1 shows 1% resistor divider values for some common output voltages with a resistor divider current of 5a. table 1. output voltage resistor divider valves v out (v) r1 (k) r2 (k) 1.2 118 118 1.5 121 182 1.8 124 249 2.5 115 365 3 124 499 3.3 124 562 5 115 845 bypass capacitance and output voltage noise the LT3050 regulator provides low output voltage noise over the 10hz to 100khz bandwidth while operating at full load with the addition of a bypass capacitor from the ref/byp pin to gnd. a good quality, low leakage capacitor is recommended. this capacitor bypasses the reference of the regulator, providing a low frequency noise pole for the internal reference. the noise pole provided by this bypass capacitor decreases the output voltage noise to as low as 30v rms with the addition of a 10nf bypass capacitor when the output voltage is 0.6v. for higher output voltages (generated by using a resistor divider), the output voltage noise increases proportionately. higher values of output voltage noise are often measured if care is not exercised with regard to circuit layout and testing. crosstalk from nearby traces induces unwanted noise onto the LT3050s output. power supply ripple rejection must also be considered. the LT3050 regulator does not have unlimited power supply rejection and passes a small portion of the input noise through to the output. during start-up, the internal reference will soft-start the reference if a bypass capacitor is present. regulator start- up time is directly proportional to the size of the bypass capacitor, slowing to 5.5ms with a 10nf bypass capacitor and 2.2f output capacitor. applications information output capacitance and transient response the LT3050 regulator is stable with a wide range of output capacitors. the esr of the output capacitor affects stability, most notably with small capacitors. use a minimum output capacitor of 2.2f to prevent oscillations. the LT3050 is a micropower device and output load transient response is a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. bypass capacitors, used to decouple individual components powered by the LT3050, increase the effective output capacitor value. for applications with large load current transients, a low esr ceramic capacitor in parallel with a bulk tantalum capacitor often provides an optimally damped response. give extra consideration to the use of ceramic capacitors. manufacturers make ceramic capacitors with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics are speci? ed with eia temperature characteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics provide high c-v products in a small package at low cost, but exhibit strong voltage and temperature coef? cients, as shown in figures 2 and 3. when used with a 5v regulator, a 16v 10f y5v capacitor can exhibit an effective value as low as 1f to 2f for the dc bias voltage applied, and over the operating temperature range. the x5r and x7r dielectrics yield much more stable characteristics and are more suitable for use as the output capacitor. the x7r type works over a wider temperature range and has better temperature stability, while the x5r is less expensive and is available in higher values. care still must be exercised when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be signi? cant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be veri? ed.
LT3050 16 3050f applications information dc bias voltage (v) change in value (%) 3050 f02 20 0 C20 C40 C60 C80 C100 0 4 8 10 26 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f temperature (c) C50 40 20 0 C20 C40 C60 C80 C100 25 75 3050 f03 C25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f figure 2. ceramic capacitor dc bias characteristics figure 3. ceramic capacitor temperature characteristics voltage and temperature coef? cients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to technical stress, similar to the way a piezoelectric accelerometer or microphone works. for a ceramic capacitor, the stress is induced by vibrations in the system or thermal transients. the resulting voltages produced cause appreciable amounts of noise. a ceramic capacitor produced the trace in figure 4 in response to light tapping from a pencil. similar vibration induced behavior can masquerade as increased output voltage noise. figure 4. noise resulting from tapping on a ceramic capacitor overload recovery like many ic power regulators, the LT3050 has safe operating area protection. the safe area protection decreases current limit as input-to-output voltage increases, and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. the LT3050 provides some output current at all values of input-to-output voltage up to the device breakdown. when power is ? rst applied, the input voltage rises and the output follows the input; allowing the regulator to start-up into very heavy loads. during start-up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. with a high input voltage, a problem can occur wherein the removal of an output short will not allow the output to recover. other regulators, such as the lt1083/lt1084/ lt1085 family and lt1764a also exhibit this phenomenon, so it is not unique to the LT3050. the problem occurs with a heavy output load when the input voltage is high and the output voltage is low. common situations are: immediately after the removal of a short-circuit or if the shutdown pin is pulled high after the input voltage is already turned on. the load line for such a load intersects the output current curve at two points. if this happens, there are two stable output operating points for the regulator. with this double intersection, the input power supply needs to be cycled down to zero and brought up again to make the output recover. 10ms/div v out 1mv/div 3050 f04 v out = 5v c out = 10f c ref/byp = 10nf
LT3050 17 3050f applications information thermal considerations the LT3050s maximum rated junction temperature of 125c limits its power handling capability. two components comprise the power dissipated by the device: 1. output current multiplied by the input/output voltage differential: i out ? (v in C v out ), and 2. gnd pin current multiplied by the input voltage: i gnd ? v in gnd pin current is determined using the gnd pin current curves in the typical performance characteristics section. power dissipation equals the sum of the two components listed above. the LT3050 regulator has internal thermal limiting that protects the device during overload conditions. for continuous normal conditions, do not exceed the maximum junction temperature of 125c. carefully consider all sources of thermal resistance from junction-to-ambient including other heat sources mounted in proximity to the LT3050. the undersides of the LT3050 dfn and msop packages have exposed metal from the lead frame to the die attachment. these packages allow heat to directly transfer from the die junction to the printed circuit board metal to control maximum operating junction temperature. the dual-in-line pin arrangement allows metal to extend beyond the ends of the package on the topside (component side) of a pcb. connect this metal to gnd on the pcb. the multiple in and out pins of the LT3050 also assist in spreading heat to the pcb. for surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through-holes also can spread the heat generated by power devices. the following tables list thermal resistance as a function of copper area in a ? xed board size. all measurements were taken in still air on a four-layer fr-4 board with one ounce solid internal planes and two ounce external trace planes with a total board thickness of 1.6mm. for further information on thermal resistance and using thermal information, refer to jedec standard jesd51, notably jesd51-12. table 1. msop measured thermal resistance copper area board area thermal resistance (junction-to-ambient) topside backside 2500 sq mm 2500 sq mm 2500 sq mm 40c/w 1000 sq mm 2500 sq mm 2500 sq mm 41c/w 225 sq mm 2500 sq mm 2500 sq mm 43c/w 100 sq mm 2500 sq mm 2500 sq mm 45c/w table 2. dfn measured thermal resistance copper area topside board area thermal resistance (junction-to-ambient) 2500 sq mm 2500 sq mm 44c/w 1000 sq mm 2500 sq mm 45c/w 225 sq mm 2500 sq mm 47c/w 100 sq mm 2500 sq mm 49c/w calculating junction temperature example: given an output voltage of 5v, an input voltage range of 12v 5%, a maximum output current range of 75ma and a maximum ambient temperature of 85c, what will the maximum junction temperature be? the power dissipated by the device equals: i out(max) * (v in(max) C v out ) + i gnd * v in(max) where, i out(max) = 75ma v in(max) = 12.6v i gnd at (i out = 75ma, v in = 12v) = 1.5ma so, p = 75ma ? (12.6v - 5v) + 1.5ma ? 12.6v = 0.589w using a dfn package, the thermal resistance ranges from 44c/w to 49c/w depending on the copper area. so the junction temperature rise above ambient approximately equals: 0.589w ? 49c/w = 28.86c the maximum junction temperature equals the maximum ambient temperature plus the maximum junction temperature rise above ambient or: t jmax = 85c + 28.86c = 113.86c
LT3050 18 3050f applications information protection features the LT3050 incorporates several protection features that make it ideal for use in battery-powered circuits. in addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device also protects against reverse-input voltages, reverse-output voltages and reverse output-to- input voltages. current limit protection and thermal overload protection protect the device against current overload conditions at the output of the device. for normal operation, do not exceed a junction temperature of 125c. the LT3050 in pin withstands reverse voltages of 50v. the device limits current ? ow to less than 300a (typically less than 10a) and no negative voltage appears at out. the device protects both itself and the load against batteries that are plugged in backwards. the shdn pin cannot be driven below gnd unless tied to the in pin. if the shdn pin is driven below gnd while in is powered, the output may turn on. shdn pin logic cannot be referenced to a negative rail. the LT3050 incurs no damage if its output is pulled below ground. if the input is left open-circuit or grounded, the output can be pulled below ground by 50v. no current ? ows through the pass transistor from the output. however, current ? ows in (but is limited by) the resistor divider that sets the output voltage. current ? ows from the bottom resistor in the divider and from the adj pins internal clamp through the top resistor in the divider to the external circuitry pulling out below ground. if the input is powered by a voltage source, the output sources current equal to its current limit capability and the LT3050 protects itself by thermal limiting. in this case, grounding the shdn pin turns off the device and stops the output from sourcing current. figure 5. reverse output current v out (v) i out (a) 1.0 0.3 0.6 0.7 0.8 0.9 0.4 0.5 0.1 0.2 3050 f05 0 0 1020304050 all pins grounded except for out
LT3050 19 3050f package description 2.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of packag 0.40 0.10 bottom viewexposed pad 0.64 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.39 0.10 (2 sides) 3.00 0.10 (2 sides) 1 6 12 7 pin 1 bar top mark (see note 6) 0.200 ref 0 C 0.05 (ddb12) dfn 0106 rev ? 0.23 0.05 0.45 bsc pin 1 r = 0.20 or 0.25 s 45 chamfer 0.25 0.05 2.39 0.05 (2 sides) recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.64 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.45 bsc msop (mse12) 0608 rev b 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 C?0.38 (.009 C .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail b 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 p 0.102 (.112 p .004) 2.845 p 0.102 (.112 p .004) 4.039 p 0.102 (.159 p .004) (note 3) 1.651 p 0.102 (.065 p .004) 0.1016 p 0.0508 (.004 p .002) 123456 3.00 p 0.102 (.118 p .004) (note 4) 0.406 p 0.076 (.016 p .003) ref 4.90 p 0.152 (.193 p .006) detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) 0.42 p 0.038 (.0165 p .0015) typ 0.65 (.0256) bsc 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max mse package 12-lead plastic msop exposed die pad (reference ltc dwg # 05-08-1666 rev b) ddb package 12-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1723 rev ?)
LT3050 20 3050f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 1209 ? printed in usa related parts typical application part number description comments lt1761 100ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, thinsot package lt1762 150ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, ms8 package lt1763 500ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, so-8 package lt1962 300ma, low noise ldo 270mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, ms8 package lt1963/a 1.5a low noise, fast transient response ldo 340mv dropout voltage, low noise: 40v rms , v in = 2.5v to 20v, a version stable with ceramic capacitors, to-220, dd-pak, sot-223 and so-8 packages lt1965 1.1a, low noise, low dropout linear regulator 290mv dropout voltage, low noise: 40v rms , v in : 1.8v to 20v, v out : 1.2v to 19.5v, stable with ceramic capacitors, to-220, dd-pak, msop and 3 3 dfn packages lt3008 20ma, 45v, 3ua i q micropower ldo 300mv dropout voltage, low i q : 3a, v in = 2.0v to 45v, v out = 0.6v to 39.5v; thinsot and 2mm 2mm dfn-6 packages lt3009 20ma, 3ua i q micropower ldo 280mv dropout voltage, low i q : 3a, v in = 1.6v to 20v, thinsot and sc-70 packages lt3010 50ma, high voltage, micropower ldo v in : 3v to 80v, v out : 1.275v to 60v, vdo = 0.3v, i q = 30a, isd < 1a, low noise: <100v rms , stable with 1f output capacitor, exposed ms8 package lt3011 50ma, high voltage, micropower ldo with pwrgd v in : 3v to 80v, v out : 1.275v to 60v, vdo = 0.3v, i q = 46a, isd < 1a, low noise: <100v rms , power good, stable with 1f output capacitor, 3 3 dfn-10 and exposed ms12e packages lt3012 250ma, 4v to 80v, low dropout micropower linear regulator v in : 4v to 80v, v out : 1.24v to 60v, vdo = 0.4v, i q = 40a, isd < 1a, tssop-16e and 4mm 3mm dfn-12 packages lt3013 250ma, 4v to 80v, low dropout micropower linear regulator with pwrgd v in : 4v to 80v, v out : 1.24v to 60v, vdo = 0.4v, i q = 65a, isd < 1a, power good feature; tssop-16e and 4mm 3mm dfn-12 packages lt3014/hv 20ma, 3v to 80v, low dropout micropower linear regulator v in : 3v to 80v (100v for 2ms, hv version), v out : 1.22v to 60v, vdo = 0.35v, i q = 7a, isd < 1a, thinsot and 3mm 3mm dfn-8 packages lt3060 100ma, low noise ldo with soft start 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 45v, dfn package lt3080/-1 1.1a, parallelable, low noise, low dropout linear regulator 300mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic caps, to-220, sot-223, msop and 3mm 3mm dfn packages; C1 version has integrated internal ballast resistor lt3085 500ma, parallelable. low noise, low dropout linear regulator 275mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic caps, msop-8 and 2mm 3mm dfn packages in i min i max adj gnd fault shdn i mon out ref/byp LT3050 3k (adc full scale = 3v) 1.15k (threshold = 100ma) 11.3k (threshold = 10ma) 3050 ta02 5v 2.2f 1f 0.1f 10nf 12v v in 120k to p adc 10nf 0.1f 1% 442k 1% 60.4k 5v protected antenna supply with 100ma current limit, 10ma i min

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